In a writing operation to a DRAM memory cell it may be desirable to apply a high voltage to the word line to which the cell is connected, so as to have a high gate-source voltage at the level of the cell's access transistor. This may allow, in particular, writing under good conditions while offering a relatively high refresh frequency. Thus, by way of indication, for advanced technologies, for example, technologies below 45 nanometers, in particular, 32 nanometers, obtaining a refresh frequency of 550 MHz may make it desirable to apply a line selection signal (voltage) of 2.5 volts to the word line.
Moreover, the generation of the line selection signal may be obtained based upon a combination of two control signals having a same voltage level (for example, 2.5 volts) as the voltage level desired to select the word line. These two control signals may be obtained respectively based upon two initial signals having a lower voltage level, for example, a nominal voltage level of 1 volt in a 32-nanometer technology. Finally, the generation of the two control signals having the high voltage level and the combining of these two control signals to obtain the line selection signal, are typically obtained with the aid of control circuitry comprising, in particular, voltage-elevator stages or level translators, buffer memories (“Buffers”) and control elements (“Drivers”). This circuitry includes, in particular, dual-oxide re-channel (NMOS) transistors.
In particular, for advanced technologies, the admissible nominal voltage for dual-oxide NMOS transistors is typically relatively low, for example, 1.8 volts for the 32-nanometer technology. Consequently to generate control signals having a higher voltage level than the admissible nominal voltage, for example, a level of 2.5 volts, induces stresses in NMOS transistors, and this may lead, in the very short term, to oxide breakdown of these transistors, according to a phenomenon known to the person skilled in the art as time dependent dielectric breakdown (TDDB). Thus, by way of indication, in a 32-nanometer technology, the application of 2.5 volts to the selected word lines of the memory plane may lead to oxide breakdown of the NMOS transistors after two days and a few hours.